A programmable logic device (PLD), such as for example a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), typically uses, for a given design configuration, only a fraction of the programmable multiplexer area. This provides certain advantages as the design is being debugged and optimized, because the programmable nature of the PLD permits design changes and modifications, such as to the connections between logic blocks. However, once the design is finalized, the majority of the programmable multiplexer area may be unused overhead (e.g., occupying in some cases over fifty percent of the total PLD fabric area). Thus, for example, localized defects that may exist in this unused programmable multiplexer or interconnect area may not have any effect on a specific design.
PLD test techniques may be viewed as being complicated by the programmable nature of the PLD, which can represent essentially an infinite number of specific design configurations. In general, there are no automated tools that are capable of generating test vectors for the PLD and thus, PLD test generation is a difficult task resulting in various proprietary procedures that are not uniform across the PLD industry. Consequently, this may make it difficult for users to determine an independent measure of the quality of testing for their specific design.
As an example, a conventional approach that may be employed to determine if a PLD with localized defects is functional for a specific user design uses many different test configurations of the PLD to attempt to isolate defective elements in the physical structure of the PLD. A list of defective elements may be generated and then compared to the list of elements used in the specific design to determine functionality. However, there may be a number of drawbacks with this conventional approach. First, the method to isolate the individual defective element requires a unique set of connections to that element, which are not guaranteed to match that used in the specific user design, with the result being “test coverage gaps” that will degrade product quality.
Second, the conventional approach does not use a rigorous fault sensitivity analysis and consequently, certain manifestations of the defect may not be observable even if the defective element is directly utilized in a test. For example, the test may pass a high logic level through a wire that is stuck high and conclude that the connection is not defective. Furthermore, because there is no industry standard tool to measure the resulting test coverage of this conventional approach, the precise quality of test is always uncertain and not independently verifiable.
As a result, there is a need for improved systems and methods for testing a PLD, such as for example to test a defect free PLD or a partially defective PLD for a specific user design. The systems and methods, for example, may provide techniques to fully test a specific PLD configuration, which may allow the use of a partially defective PLD that otherwise, would have been rejected by the PLD manufacturer. The systems and methods, for example, may further provide techniques to enable automated test techniques for test pattern generation for a specific PLD design and may provide for an industry standard measure of testing quality.